1. Field of the Invention
The present invention relates to a power metal oxide semiconductor transistor layout, and more particularly to a power metal oxide semiconductor transistor layout with a lower output resistance and a high current limit.
2. Description of the Related Art
Metal oxide semiconductor (MOS) transistors with very large line width are widely used as power switch of power management application. However, the long source and drain connection results in some drawbacks such as a severe voltage drop at metal connection. Moreover, the cell pitch of power device must be as small as possible so as to increase packing density. Thus, the line width of source and drain metal connection is limited. The length of line of source and drain connection is also limited by electron migration especially for limited line width. So, it is a dilemma to achieve a power MOS transistor with high current and high packing density layout.
Referring to FIG. 1, a conventional MOSFET current driver 14 is laid out to have a gate with a vertical serpentine pattern. The serpentine pattern is laid out to have a plurality of long strips 21 parallel to each other along the length of the layout of the current driver. Also, the serpentine pattern has a plurality of short strips 15 which connect the long strips to each other in such a manner to generate a long continuous gate. The serpentine pattern of the conventional layout is called vertical since the long strips 21 are laid out along the length of the layout of the current driver. The drain area 16 and source area 18 are located between the long strips 21 of the gate 20 in an interlace form. The drain metal 17 has a plurality of fingers 22 and the source metal 19 has a plurality of fingers 24. The drain fingers 22 and the source fingers 24 are laid out in such a manner that they are in an interlace relationship with each other and each drain finger 22 is located above a drain area 16 and each source finger 24 is located above a source area 18. Each drain finger 22 has plurality of contacts 26 with the drain area 16 underneath the drain finger 22. Each source finger 24 has plurality of contacts 28 with the source area 18 underneath the source finger 24. The conventional MOSFET current driver layout is prone to have shorts or defects. First of all, the long source and drain connection would result in severe voltage drop at metal connection. Moreover, the line width of source and drain metal connection is also limited by electron migration.
Referring to FIG. 2, another conventional layout of a MOSFET current driver 34 is shown. In the design of this conventional layout, the gate 40 is laid out to have a lateral serpentine pattern. The serpentine pattern is laid out to have a plurality of long strips 41 and a plurality of short strips 43. The long strips 41 are laid out parallel to each other along the width of the current driver 34. The short strips 43 are laid out to connect the long strips to each other in such a manner to generate a long continuous gate. The serpentine pattern of this design is called lateral since the long strips 41 are laid out along the width of the current driver 34. The drain areas 36 and source areas 38 are located between the long strips 41 of the gate 40 in an interlace form. Also, in the layout there are only two metal strips which substantially overlap the serpentine patterned gate; one serves as the drain metal 37 and the second serves as the source metal 39. The drain metal 37 has a plurality of drain contacts 42a, 42b, 42c, 42d, 42e, 42f and 42g and the source metal 39 has a plurality of source contacts 44a, 44b, 44c, 44d, 44e, 44f and 44g. Each drain contact is placed on a drain area 36 to connect the drain metal 37 to the drain area 36 and each source contact is placed on a source area 38 to connect the source metal 39 to the source area 38. This conventional MOSFET current driver layout also has several drawbacks. First of all, the line width of source and drain metal connection line is limited due to the source and drain connected by high resistance diffusion layer. Moreover, the line length of source and drain connection is also limited by electron migration.
In view of the drawbacks mentioned with the prior art, there is a continued need to develop new and improved power MOS transistor layout that overcome the disadvantages associated with prior art. The requirements of this invention are that it solves the problems mentioned above.